Nikhilam Sutra literally means "all from 9 and last from 10". The proposed multiplier architecture finds out the complement of the large number from its nearest base to perform the multiplication. Hence, the multiplication of...Rutuparna Panda...
In this paper we bring out a Vedic multiplier known as " Nikhilam Sutra multiplier". The ―Nikhilam Navatascaram Dasatah literally means ―All from Nine and the last from Ten. The sutra basically means start from the left most digit and begin subtracting ‗9` from each of the digits;...
Pradhan M and Panda R., "High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics", International Journal of Electronics, DOI:10.1080/00207217.2013.780298.M. Pradhan and R. Panda, "High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics," International Journal of...
Many integer operations such as multiplication, squaring, division and computing reciprocal require same order of time as multiplication .This paper describes the implementation of an 64-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array ...
M. Nisha AngelineS. Valarmathy电路与系统(英文)M. Nisha Angeline, S. Valarmathy, Implementation of N-Bit BinaryMultiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method, Scientific research publishing2016,( Sathyamangalam, India)....
In this paper an FPGA implementation of low power square and cube architectures using Nikhilam sutra have been proposed. Multipliers are extensively used in FIR filters, Microprocessors, DSP and communication applications. For higher order multiplications, a huge number of adders or compressors are to...
High Speed Vedic Multiplier UsingNikhilam Sutra with Barrel ShifterL Kishore Kumar ReddyM Venkata SubbaiahResearch & Reviews
This new method is divided in to two part first split numbers in Karatsuba forms and second is multiply them using nikhilam sutra. In this paper we are going to implement polynomial multiplication using Spartan... FPGA device. The code were written in VHDL and they were simulated and synthesi...